In the fabrication and use of field-effect transistors (FETs), it is generally known that short channel lengths yield high performance devices. Conventional photolithography is used in fabrication processes to produce high-performance FETs with submicron, i.e. in the range of 0.8-1.0 micron, channel lengths.
It is further known that FETs having channel lengths in the 0.1 micron range, when operated at very low temperatures (on the order of 77 degrees Kelvin, or lower), provide even better performance. However, with the resolution of conventional photolithography currently limited to about 0.5 micron, no process is known for the reliable, large-scale manufacture of devices incorporating the desirably shorter channel lengths.
Direct write electron beam lithography is capable of providing features in the desired sub-micron range. However, this process is slow, and not adaptable to large-scale manufacturing. X-ray lithography is also capable of providing such high resolution, but comprises a complex, expensive process which is not currently practical for large-scale manufacturing.
Another method of forming sub-micron features is the use of what is termed a "sidewall image transfer" processes. In such a process, a sub-micron sidewall element is used as a mask to transfer, by etching, the sub-micron dimension into underlying materials. See, for example, U.S. Pat. No. 4,502,914 to Trumpp et al. (assigned to the assignee of the present invention), which shows many different sidewall image transfer processes utilizing polymer materials. See also Japanese Kokai 63-307739 (by Fujitsu Ltd.) showing a similar process. Such processes are capable of fabricating features even smaller than those available with conventional photolithography. However, as the feature dimensions approach the 0.1 micron range, the process variations, particularly those related to the etching, are too large to provide the uniformity and reproducibility required for manufacturing.
Yet another method of forming FET devices includes the use of a conductive sidewall as the actual FET gate. See, for example, Japanese Kokai 57-42151 (by Fujitsu K. K.) wherein a polycrystalline sidewall is utilized as an FET gate. U.S. Pat. No. 4,419,809 to Riseman et al. (assigned to the assignee of the present invention) shows a similar process, and further includes the use of additional sidewalls, formed on the sidewall gate, to act as successive masks for dopant implants which control the effective channel length of the completed device. See also U.S. Pat. No. 4,312,680 to Hsu wherein the gate sidewall is formed by lateral diffusion with an etch limiting element from an mesa/source. Selective etching is then used to leave the sidewall.
One problem encountered in the use of such "sidewall gates" as are shown in Fujitsu K. K., Hsu, and Riseman et al. is that of the gates themselves being asymmetrical. More specifically, Fujitsu K. K. and Riseman et al. teach the use of a sidewall gate formed by conformal deposition of a thin, conductive layer, and directional etching whereby to remove horizontal features and leave vertical sidewalls. Hsu teaches doping of the sidewall, followed by selective etching to leave the sidewall. The vertical sidewalls formed by these processes exhibit a characteristic "shoulder," or sloping upper corner, inherently formed by the etching step. This asymmetrical structure of the gate makes it impossible to form symmetrical transistors, resulting in reduced-performance devices.
A further problem encountered in the formation of such sidewall gate structures is that of unequal etching of the surfaces adjoining the gates. More specifically, upon the completion of the etch step used to form the sidewall gates, it is necessary to remove the mesa or form on which the sidewall was formed. The etch used to remove the mesa also removes part of the exposed surface not covered by the mesa and adjoining the sidewall gate. This unevenness in the surfaces adjoining the gate results in an asymmetrical device structure providing less than optimum performance.
No prior art process is known to the present inventors which is suitable in reliability, affordability, and reproducibility for the large-scale fabrication of sub-micron channel FETs.